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Polyphase Interpolation Filter
Interpolator Latency
The latency primarily depends on the filter size; that is number of physical taps equal TAPS/L. The following
formula describes the latency expressed in the number of clock cycles:
Latency = (TAPS/L + 2) clock cycles
EQ 9
If RCLK is used to diminish the output sample rate, the formula stays the same but the latency now is
measured in RCLK cycles:
Latency = (TAPS/L + 2) RCLK cycles
The latency also depends on how many hard MAC rows (columns) the filter implementation takes and a
part-dependent number of pipeline registers used to cross inter-row or column space. For convenience the
core calculates the overall latency and prints it out during simulation. Look for the line “LATENCY = x
CLOCK or RCLK cycles”.
Any FIR filter convolves a series of data samples with a set of filter coefficients. Thus, the filter starts
generating valid results only after getting enough data samples and coefficients. Upon power-on or
swapping coefficient pages, CoreFIR holds the FIRO_VALID signal inactive until it gets TAPS valid data
samples. Here "valid data samples" means the data coming in response to the active READY signal.
46
CoreFIR v8.5 Handbook
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COREFIR-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator
COREMP7 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreMP7
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